`include "defines.v"

module regfile (
    input  wire                         clock,
    input  wire                         reset,
    
    //read port
	input  wire                         rs1_r_en,
    input  wire [`REGFILE_ADDR_LEN-1:0] rs1_r_addr,
    output wire [`XLEN-1:0]             rs1_r_data,

	input  wire                         rs2_r_en,
    input  wire [`REGFILE_ADDR_LEN-1:0] rs2_r_addr,
    output wire [`XLEN-1:0]             rs2_r_data,

    //write port
    input  wire                         rd_w_en,
    input  wire [`REGFILE_ADDR_LEN-1:0] rd_w_addr,
    input  wire [`XLEN-1:0]             rd_w_data,

	//sim
	output reg [`XLEN-1:0] rf [31: 0]  //TODO:delete before soc
);

	//reg [63: 0] rf [31: 0];         //TODO:add before soc
	//----------Write Port----------//
	always @(posedge clock) begin
	    if (reset) begin
	        rf[ 0] <= `ZERO_WORD;
			rf[ 1] <= `ZERO_WORD;
			rf[ 2] <= `ZERO_WORD;
			rf[ 3] <= `ZERO_WORD;
			rf[ 4] <= `ZERO_WORD;
			rf[ 5] <= `ZERO_WORD;
			rf[ 6] <= `ZERO_WORD;
			rf[ 7] <= `ZERO_WORD;
			rf[ 8] <= `ZERO_WORD;
			rf[ 9] <= `ZERO_WORD;
			rf[10] <= `ZERO_WORD;
			rf[11] <= `ZERO_WORD;
			rf[12] <= `ZERO_WORD;
			rf[13] <= `ZERO_WORD;
			rf[14] <= `ZERO_WORD;
			rf[15] <= `ZERO_WORD;
			rf[16] <= `ZERO_WORD;
			rf[17] <= `ZERO_WORD;
			rf[18] <= `ZERO_WORD;
			rf[19] <= `ZERO_WORD;
			rf[20] <= `ZERO_WORD;
			rf[21] <= `ZERO_WORD;
			rf[22] <= `ZERO_WORD;
			rf[23] <= `ZERO_WORD;
			rf[24] <= `ZERO_WORD;
			rf[25] <= `ZERO_WORD;
			rf[26] <= `ZERO_WORD;
			rf[27] <= `ZERO_WORD;
			rf[28] <= `ZERO_WORD;
			rf[29] <= `ZERO_WORD;
			rf[30] <= `ZERO_WORD;
			rf[31] <= `ZERO_WORD;
	    end
	    else if (rd_w_en & (|rd_w_addr)) rf[rd_w_addr] <= rd_w_data;
	end

	//----------Read Port----------//
	assign rs1_r_data = (reset | ~rs1_r_en)      ?  `ZERO_WORD  :
	                    (rs1_r_addr == 5'b00000) ?  `ZERO_WORD  :  rf[rs1_r_addr]  ;

	assign rs2_r_data = (reset | ~rs2_r_en)      ?  `ZERO_WORD  :
	                    (rs2_r_addr == 5'b00000) ?  `ZERO_WORD  :  rf[rs2_r_addr]  ;

endmodule
